The present invention relates to an ATM (Asynchronous Transfer Mode) switch and, more particularly, to an ATM switch having a shared cell memory that simplifies cell queuing control.
A conventional example of cell queuing control in an ATM switch having a shared cell memory will be described with reference to FIGS. 5, 6, and 7.
According to an ATM switch of this type, as shown in FIG. 5, a shared cell memory 102 serving as a shared buffer is provided for an ATM switch 101 to perform read/write control such that cells from a plurality of input lines 103 are stored in available cell areas of the shared cell memory 102, and a series of cells are output in units of the line numbers of output lines 104.
The following two schemes are available as stored cell queuing control schemes that can realize control of cells from the shared cell memory in units of output lines and in the output order. The first scheme is a scheme of performing cell connection by using an address chain using pointers. As shown in FIG. 6, addresses (pointers) 106 in the shared cell memory 102 at which the next cells to be read out are stored in correspondence with cells 105 are stored. The second scheme is a scheme of performing address chaining by using a pseudo-address chain. As shown in FIG. 7, only the cells 105 are stored in available cell areas in the shared cell memory 102, and cell storage address managing sections 108 are used to store headers 107 and the like of the cells 105 in units of output lines and in the output order, thus performing queuing control
In the conventional ATM switch designed to perform queuing control using the pointers 106 in FIG. 6, when the cells 105 are to be stored, available cell areas in the shared cell memory 102 are hunted in units of cells, and the cells 105 are written in the hunted areas. In addition to these operations, control must be performed to connect the cell areas by using the pointers 106. When a given cell 105 is to be transmitted, the pointer 106 of the previously readout cell 105 is checked, and the cell area designated by the checked pointer 106 is selected to read out the cell 105 therefrom. In addition to these operations, control must be performed to hold the pointer 106 of the readout cell 105 for the next check.
In the conventional ATM switch designed to perform queuing control using a pseudo-address chain using the headers 107 in FIG. 7, when the cells 105 are to be stored, idle cell areas in the shared cell memory 102 are hunted in units of cells, and the cells 105 are written in the hunted cell areas. In addition to these operations, control must be performed to store the headers 107 detected from the cells 105 in the cell storage address managing sections 108 provided by the same number as that of the output lines in units of output lines and in the output order.
As described above, both the conventional ATM switches designed to perform queuing control require complicated control, resulting in complicated system configurations.